Marvell Announces Breakthrough Co-Packaged Optics Architecture for Custom AI Accelerators

Marvell Technology's CPO Innovation - Marvell Technology advances its custom XPU architecture with co-packaged optics (CPO) technology, enabling seamless integration into next-generation custom XPUs and scaling AI server performance [1] - The custom AI accelerator architecture combines XPU compute silicon, HBM, and Marvell 3D SiPho Engines, eliminating the need for electrical signals to leave the XPU package, achieving 100X longer connections than electrical cabling [2] - CPO technology integrates optical components directly within a single package, minimizing electrical path length, reducing signal loss, and enhancing data throughput with high-bandwidth silicon photonics optical engines [3] Marvell's 3D SiPho Engine - The Marvell 3D SiPho Engine supports 200Gbps electrical and optical interfaces, delivering 2x the bandwidth, 2x the input/output bandwidth density, and 30% lower power per bit compared to 100G interfaces [4] - Marvell's silicon photonics technology has been deployed for over eight years, logging over 10 billion field hours, and is qualified for high-volume production by leading hyperscalers [5] Marvell's Interconnect Portfolio - Marvell's interconnect portfolio includes high-performance SerDes, die-to-die technology IP, PCIe retimers, CXL devices, Active Electrical Cable, Active Optical Cable digital signal processors, PAM optical DSPs, and coherent DSPs for data center interconnect modules [6] Industry Impact and Future Growth - Marvell's CPO architecture enables cloud hyperscalers to develop custom XPUs, increasing AI server density from tens within a rack to hundreds across multiple racks [7] - Industry experts forecast CPO port shipments to grow from less than 50 thousand today to over 18 million by 2029, with Marvell positioned to enable hyperscalers to unlock CPO's potential [8] Executive Insights - Marvell executives highlight the importance of CPO in scaling AI server performance, addressing increasing bandwidth demands, and optimizing power consumption for next-generation accelerated infrastructure [8]