Soitec and PSMC collaborate on ultra-thin TLT technology for nm-scale 3D stacking

Core Insights - Soitec and Powerchip Semiconductor Manufacturing Corporation (PSMC) have announced a strategic collaboration to develop ultra-thin Transistor Layer Transfer (TLT) technology for advanced 3D chip stacking [1][2] - The collaboration aims to enhance semiconductor designs, making chips more powerful, compact, and energy-efficient, with applications in smartphones, AI devices, and autonomous driving systems [3][4] Company Overview - Soitec is a leader in innovative semiconductor materials, generating sales of €0.9 billion in fiscal year 2024-2025 and holding over 4,000 patents [8] - PSMC is the seventh-largest pure-play foundry globally, with a production capacity of over 2.1 million 12-inch equivalent wafers annually and a new fab in Taiwan with a planned capacity of 1.2 million wafers [11] Technology Details - The TLT technology enables the stacking of multiple transistor layers vertically, supporting advanced 3D transistor architectures and optimizing power performance [5][6] - Soitec's TLT substrate utilizes Smart Cut™ technology and infrared laser release processing, allowing for ultra-thin semiconductor layers ranging from 5nm to 1µm [6] Collaboration Impact - The partnership reflects a commitment to advancing 3D integration and meeting the industry's demand for faster, more energy-efficient chips [4][7] - The collaboration builds on existing France-Taiwan initiatives in AI and semiconductor technologies, enhancing global cooperation in the sector [7]